In integrated circuit ("IC") chips, capacitors have many uses. As one example, an individual memory cell within an array of dynamic random access memories ("DRAMs") may comprise a capacitor coupled to a transistor. A binary one (1) is written to the DRAM cell by turning on the transistor and passing current therethrough to charge the capacitor. The storage state of the memory cell is read by turning on the transistor and reading the voltage level to which the capacitor is charged. If the voltage level exceeds a predetermined threshold, then a binary one is read, otherwise a binary zero is read. In such applications, it is desirable for the capacitor to store a large charge for a long time, making high capacitance and low leakage advantageous characteristics.
In early DRAMS, simple plate capacitors were used in the memory cells. A conductor, followed by a dielectric, followed by another conductor were deposited on the substrate of the IC chip forming a plate capacitor. As memory densities increased and memory cell size correspondingly decreased, this technology proved to occupy an impractical amount of space. One alternate technology was trench technology in which a trench was etched out of a silicon substrate, the side walls thereof oxidized to form a dielectric, and the trench filled with a conductor to thereby form a capacitor. Problems arose with this technology, however, as memory densities increased because the width of the trenches (i.e., cell size) decreased and the trench depths correspondingly increased to maintain capacitance. Quickly, the necessary trench depths are becoming impractical to achieve due to aspect ratio limitations of etching processes used to form the trenches. As is well known, narrow deep trenches are difficult to etch.
As trench capacitor technology developed, the plate, or stacked capacitor technology advanced as well. One type of stacked capacitor is a stud stacked capacitor in which a polysilicon stud is defined, coated with oxide (i.e., a dielectric), and then coated with a conformal layer of polysilicon. Unfortunately, the stud capacitor has low capacitance. Another stacked capacitor is a multiple layer planar stacked capacitor that includes alternating layers of polysilicon and oxide. The polysilicon layers are all connected on one side of the stack and the oxide is removed leaving horizontal, freestanding polysilicon "fingers." These "fingers" are oxidized and additional polysilicon is deposited between the fingers forming a second capacitor plate. Unfortunately, while freestanding, the fingers are very unstable such that the total number of possible layers is limited and a corresponding limitation on capacitance results.
In chimney capacitor structures, similar polysilicon "fingers" are used, however they typically comprise cylinders and are oriented vertically. Forming chimney capacitors conventionally involves depositing a mandrel, fabricating the polysilicon fingers with the use of the mandrel, and removing the mandrel leaving the vertical polysilicon fingers freestanding. A thin oxide is then deposited on the fingers as a dielectric, and the spaces between the fingers are filled with polysilicon forming a second capacitor plate that is electrically connected from above. A freestanding chimney capacitor is thus formed.
Conventional chimney capacitors have good capacitance and leakage characteristics; however, they are not without problems. Electrical contact to one of the plates of a chimney capacitors is conventionally made to the upper surface of a chimney capacitor. Wiring must therefore be performed above the chimney capacitor and circuitry located therebelow. This causes planarization concerns for the subsequent wiring levels, increases the number of processes necessary to complete wiring of the IC chip containing the chimney capacitors and makes use of an available upper wiring level. Thus, the wireability of IC chips containing conventional chimney capacitors is limited.
During fabrication, physical stability of the freestanding structures is a crucial problem. As the chimney capacitor becomes higher, it becomes less stable and is more likely to collapse during the fabrication processes. Further, it is often desirable to deposit a thick conformal layer of oxide over the chimney capacitors on an IC chip and planarize the oxide. The planar upper surface of the oxide simplifies wiring of the devices. However, the topography of chimney capacitors on a DRAM IC chip causes planarization problems as the chimneys become higher. Specifically, the height differential between the chimneys and surrounding logic areas impedes both the deposition, and planarization of a conformal oxide layer. Even if the planarized insulating layer is established, various openings down to the transistors of the DRAM chip must then be provided for wiring thereof. Etching these openings becomes problematic as the chimney height (and corresponding insulating layer thickness) increases. This is due to high aspect ratio etch problems.
To summarize, the overall wireability, height and corresponding capacitance of conventional chimney capacitor structures are limited. The present invention is directed toward providing solutions for the above-noted problems.